17847948. STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME
Organization Name
Inventor(s)
Jeong Uk Kang of Seongnam-si (KR)
Hyun Jin Choi of Suwon-si (KR)
STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17847948 titled 'STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THE SAME
Simplified Explanation
The abstract describes a storage controller that writes data to a memory cell multiple times. It includes a write amplification manager and a central processing unit. The write amplification manager checks if the data is invalid before performing the multiple programming of the memory cell. The central processing unit avoids the final programming if the data is invalid.
- The storage controller writes data to a memory cell multiple times.
- It includes a write amplification manager and a central processing unit.
- The write amplification manager checks if the data is invalid before programming the memory cell multiple times.
- The central processing unit skips the final programming if the data is invalid.
Potential Applications
- Data storage systems
- Solid-state drives (SSDs)
- Flash memory devices
Problems Solved
- Reduces write amplification in storage systems
- Prevents unnecessary programming of memory cells with invalid data
Benefits
- Improved efficiency and performance of storage systems
- Extends the lifespan of memory cells by avoiding unnecessary programming
Original Abstract Submitted
A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times, where N is a positive integer greater than 1, includes a write amplification manager and a central processing unit. The write amplification manager checks whether the first data is invalid data before an N programming of the first memory cell is performed, and the central processing unit does not perform the N-th programming of the first memory cell when the first data is the invalid data.
