17847089. MEMORY DEVICE WITH LATCH-BASED NEURAL NETWORK WEIGHT PARITY DETECTION AND TRIMMING simplified abstract (Western Digital Technologies, Inc.)

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MEMORY DEVICE WITH LATCH-BASED NEURAL NETWORK WEIGHT PARITY DETECTION AND TRIMMING

Organization Name

Western Digital Technologies, Inc.

Inventor(s)

Daniel Joseph Linnen of Naperville IL (US)

Ramanathan Muthiah of Bangalore (IN)

Kirubakaran Periyannan of Saratoga CA (US)

MEMORY DEVICE WITH LATCH-BASED NEURAL NETWORK WEIGHT PARITY DETECTION AND TRIMMING - A simplified explanation of the abstract

This abstract first appeared for US patent application 17847089 titled 'MEMORY DEVICE WITH LATCH-BASED NEURAL NETWORK WEIGHT PARITY DETECTION AND TRIMMING

Simplified Explanation

The abstract describes latch-based methods and apparatus for detecting bit flip errors in neural network weight data within a non-volatile memory (NVM) array. The methods are particularly useful for floating point number values.

  • The methods detect parity errors in neural network weights and set the erroneous weight to zero, preventing it from significantly affecting the network.
  • The procedures described are linear and do not require logic decisions, making them efficient and straightforward.
  • The methods also assess the degradation of the NVM array based on collected parity bit data in the latches.
  • Multiple plane and multiple die NVM array implementations are described, enabling massive parallel processing.

Potential Applications

  • Artificial intelligence and machine learning systems
  • Neural networks and deep learning models
  • Non-volatile memory arrays used in computing and storage devices

Problems Solved

  • Detection and mitigation of bit flip errors in neural network weight data
  • Prevention of erroneous values from significantly affecting the network, especially in floating-point weight values
  • Efficient and linear procedures that do not require complex logic decisions

Benefits

  • Improved accuracy and reliability of neural networks
  • Enhanced performance and stability of artificial intelligence systems
  • Efficient and straightforward methods for detecting and handling bit flip errors in NVM arrays


Original Abstract Submitted

Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network, particularly in situations where the bit flip would otherwise affect the magnitude of a floating-point weight value. The exemplary latch-based procedures described herein are linear procedures that do not require logic decisions. Procedures are also described that assess an amount of degradation in the NVM array based on parity bit data collected in the latches. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.

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