17847039. NON-VOLATILE MEMORY DIE WITH LATCH-BASED MULTIPLY-ACCUMULATE COMPONENTS simplified abstract (Western Digital Technologies, Inc.)

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NON-VOLATILE MEMORY DIE WITH LATCH-BASED MULTIPLY-ACCUMULATE COMPONENTS

Organization Name

Western Digital Technologies, Inc.

Inventor(s)

Daniel Joseph Linnen of Naperville IL (US)

Ramanathan Muthiah of Bangalore (IN)

Kirubakaran Periyannan of Saratoga CA (US)

NON-VOLATILE MEMORY DIE WITH LATCH-BASED MULTIPLY-ACCUMULATE COMPONENTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17847039 titled 'NON-VOLATILE MEMORY DIE WITH LATCH-BASED MULTIPLY-ACCUMULATE COMPONENTS

Simplified Explanation

The abstract of this patent application describes latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile memory (NVM) array. The MAC procedures are linear and do not require logic branches. The MAC operation uses a set of linear MAC stages, where each stage processes MAC operations for one bit of a first multi-bit multiplicand multiplied against a second multi-bit multiplicand. The MAC procedures can be used in a neural network feedforward procedure, where the first multiplicand is a synaptic weight and the second multiplicand is an activation value. Multiple plane and multiple die NVM array implementations are also discussed for massive parallel processing.

  • Latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile memory (NVM) array.
  • Linear MAC procedures that do not require logic branches.
  • Each linear MAC stage processes MAC operations for one bit of a first multi-bit multiplicand multiplied against a second multi-bit multiplicand.
  • MAC procedures can be used in a neural network feedforward procedure.
  • First multiplicand is a synaptic weight and the second multiplicand is an activation value.
  • Multiple plane and multiple die NVM array implementations for massive parallel processing.

Potential Applications

  • Neural networks and deep learning applications.
  • High-performance computing and parallel processing.
  • Artificial intelligence and machine learning systems.
  • Data analytics and pattern recognition.
  • Signal processing and image recognition.

Problems Solved

  • Efficient implementation of multiply-accumulate (MAC) operations on a non-volatile memory (NVM) array.
  • Elimination of logic branches in MAC procedures for improved performance.
  • Enabling massive parallel processing for neural networks and other applications.

Benefits

  • Improved performance and efficiency in MAC operations.
  • Simplified and linear MAC procedures without logic branches.
  • Integration of MAC operations on the die of a non-volatile memory (NVM) array.
  • Enablement of massive parallel processing for faster computation.
  • Potential for lower power consumption and reduced latency.


Original Abstract Submitted

Latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile memory (NVM) array are disclosed. The exemplary latch-based MAC procedures described herein are linear procedures that do not require logic branches. In one example, the MAC operation uses a set of linear MAC stages, wherein each linear stage processes MAC operations corresponding to one bit of a first multi-bit multiplicand being multiplied against a second multi-bit multiplicand. Examples are provided wherein the MAC procedures are performed as part of a neural network feedforward procedure where the first multiplicand is a synaptic weight and the second multiplicand is an activation value. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.

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