17846777. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Hyeonjeong Hwang of Cheonan-si (KR)

Minjung Kim of Cheonan-si (KR)

Jongyoun Kim of Seoul (KR)

Seokhyun Lee of Hwaseong-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17846777 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The patent application describes semiconductor packages and methods for fabricating them. These packages include multiple layers and components such as substrates, semiconductor chips, redistribution layers, and through electrodes.

• The semiconductor package consists of a lower substrate, a lower semiconductor chip, a redistribution layer, an upper semiconductor chip, and a through electrode.
• The lower substrate is made up of a first dielectric layer, a first conductive pattern with a wiring pattern and an under-bump pattern, a second dielectric layer, and a second conductive pattern.
• The under-bump pattern of the lower substrate has a first head part and a first tail part, with the first head part having an inclined lateral surface on the first dielectric layer.
• The second conductive pattern of the lower substrate has a perpendicular lateral surface on the second dielectric layer.

Potential applications of this technology:

• Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
• Integrated circuits and microprocessors used in various industries including automotive, aerospace, and telecommunications.

Problems solved by this technology:

• Provides a simplified and efficient method for fabricating semiconductor packages.
• Enables the integration of multiple components and layers in a compact and reliable manner.
• Improves the performance and functionality of electronic devices by enhancing the connectivity and electrical properties of the semiconductor package.

Benefits of this technology:

• Enhanced reliability and durability of semiconductor packages.
• Improved electrical performance and signal transmission.
• Compact and space-saving design for electronic devices.
• Cost-effective manufacturing process for semiconductor packages.

Original Abstract Submitted

Disclosed are semiconductor packages and fabrication methods thereof. The semiconductor package may include a lower substrate, a lower semiconductor chip, a redistribution layer, an upper semiconductor chip, and a through electrode. The lower substrate may include a first dielectric layer, a first conductive pattern having a wiring pattern and an under-bump pattern, a second dielectric layer, and a second conductive pattern. The under-bump pattern may include a first head part and a first tail part. The first head part may have a first lateral surface on the first dielectric layer that is inclined to a top surface of the first dielectric layer. The second conductive pattern may have a second lateral surface on the second dielectric layer that is perpendicular to a top surface of the second dielectric layer.