17841184. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17841184 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes multiple semiconductor chips stacked on top of each other. The chips are connected using connection bumps and are covered by a protection layer and a mold layer. The protection layer is located between the mold layer and the connection bumps.
- The semiconductor package includes multiple semiconductor chips stacked in a vertical direction.
- Connection bumps are used to connect the chips together and to the lower chip.
- A protection layer covers the connection bumps to provide additional protection.
- A mold layer covers the lateral surfaces of the chips and extends between the bottommost chip and the lower chip.
Potential Applications
- This technology can be used in various electronic devices that require compact and efficient semiconductor packaging.
- It can be applied in mobile phones, tablets, laptops, and other portable electronic devices.
- It can also be used in automotive electronics, medical devices, and industrial equipment.
Problems Solved
- The semiconductor package solves the problem of limited space in electronic devices by stacking multiple chips vertically.
- It provides a reliable and efficient method of connecting the chips together and to the lower chip.
- The protection layer and mold layer offer enhanced protection to the connection bumps and the chips.
Benefits
- The stacked semiconductor chips allow for increased functionality and performance in electronic devices.
- The compact design saves space and enables smaller and thinner devices.
- The protection layer and mold layer provide improved durability and reliability to the semiconductor package.
Original Abstract Submitted
A semiconductor package includes a lower semiconductor chip and semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip. Connection bumps are between the lower semiconductor chip and a bottommost one of the semiconductor chips and between the semiconductor chips, A protection layer covers a lateral surface of each of the connection bumps. A mold layer is on the lower semiconductor chip and covering lateral surfaces of the semiconductor chips. The mold layer extends between the bottommost one of the semiconductor chips and the lower semiconductor chip and between the semiconductor chips. The protection layer is between the mold layer and the lateral surface of each of the connection bumps.
