FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS

The abstract describes an apparatus that includes a circuit board, an active interposer, and a graphics processor die. The graphics processor die has graphics processor resources for a multi-die system on chip (SoC) device, excluding functionality implemented in a separate die. The apparatus also includes a field-programmable gate array (FPGA) with configurable hardware logic to emulate the functionality of the separate die, allowing validation of the graphics processor die separately from other dies of the multi-die SoC.

The apparatus includes a circuit board, active interposer, graphics processor die, and field-programmable gate array (FPGA).
The graphics processor die has graphics processor resources for a multi-die SoC device, excluding functionality implemented in a separate die.
The active interposer connects the graphics processor die to the circuit board via a debug package.
The FPGA has configurable hardware logic that can emulate the functionality of the separate die.
The FPGA enables silicon validation of the graphics processor die independently from other dies of the multi-die SoC.

Potential Applications

Silicon validation of graphics processor dies in multi-die SoC devices.
Testing and debugging of graphics processor functionality separately from other components of the SoC.

Problems Solved

Allows for separate validation of graphics processor dies, reducing the complexity and time required for overall SoC validation.
Enables testing and debugging of graphics processor functionality independently, facilitating faster identification and resolution of issues.

Benefits

Simplifies the validation process for multi-die SoC devices.
Reduces the time and effort required for testing and debugging graphics processor functionality.
Enables more efficient development and optimization of graphics processor designs.

Original Abstract Submitted

One embodiment provides an apparatus comprising a circuit board; an active interposer coupled with the circuit board via a debug package, and a graphics processor die coupled with the active interposer via the debug package. The graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device and excludes functionality that is implemented in a separate due of the multi-die SoC. The apparatus includes a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate functionality provided by the separate die of the multi-die SoC device, which enables silicon validation of the graphics processor die separately from other dies of the multi-die SoC.

17840211. FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS simplified abstract (Intel Corporation)

Contents

FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS

Organization Name

Inventor(s)