17840029. CONCURRENTLY FETCHING INSTRUCTIONS FOR MULTIPLE DECODE CLUSTERS simplified abstract (Intel Corporation)
CONCURRENTLY FETCHING INSTRUCTIONS FOR MULTIPLE DECODE CLUSTERS
Organization Name
Inventor(s)
Mathew Lowes of Austin TX (US)
Martin Licht of Round Rock TX (US)
Jonathan Combs of Austin TX (US)
CONCURRENTLY FETCHING INSTRUCTIONS FOR MULTIPLE DECODE CLUSTERS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17840029 titled 'CONCURRENTLY FETCHING INSTRUCTIONS FOR MULTIPLE DECODE CLUSTERS
Simplified Explanation
The abstract describes an apparatus that includes a branch prediction circuit, a fetch circuit, and two decode clusters. The branch prediction circuit predicts whether a branch is to be taken. The fetch circuit sends a first portion of a fetch region of instructions to the first decode cluster and a second portion to the second decode cluster. The first decode cluster decodes instructions in the first portion, while the second decode cluster decodes instructions in the second portion.
- The apparatus includes a branch prediction circuit to predict branch outcomes.
- A fetch circuit is used to send different portions of a fetch region to separate decode clusters.
- The first decode cluster decodes instructions in the first portion of the fetch region.
- The second decode cluster decodes instructions in the second portion of the fetch region.
Potential Applications
- This technology can be applied in microprocessors and computer architectures.
- It can improve the efficiency and performance of instruction decoding in processors.
Problems Solved
- The apparatus solves the problem of efficiently decoding instructions in a fetch region.
- It addresses the challenge of predicting branch outcomes accurately.
Benefits
- By predicting branch outcomes and distributing the decoding process, the apparatus can improve the overall performance of a processor.
- It allows for parallel decoding of instructions, which can enhance the speed and efficiency of instruction execution.
Original Abstract Submitted
In one embodiment, an apparatus comprises: a branch prediction circuit to predict whether a branch is to be taken; a fetch circuit, in a single fetch cycle, to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to the second decode cluster; the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region; and the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region. Other embodiments are described and claimed.
