17839639. MEMORY DEVICES, MEMORY SYSTEMS HAVING THE SAME, AND OPERATING METHODS THEREOF simplified abstract (Samsung Electronics Co., Ltd.)
MEMORY DEVICES, MEMORY SYSTEMS HAVING THE SAME, AND OPERATING METHODS THEREOF
Organization Name
Inventor(s)
Yonghun Kim of Hwaseong-si (KR)
Yoochang Sung of Hwaseong-si (KR)
MEMORY DEVICES, MEMORY SYSTEMS HAVING THE SAME, AND OPERATING METHODS THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 17839639 titled 'MEMORY DEVICES, MEMORY SYSTEMS HAVING THE SAME, AND OPERATING METHODS THEREOF
Simplified Explanation
The patent application describes a memory device that includes two ranks, each with memory banks and a quad skew adjustment circuit. The quad skew adjustment circuits receive a 4-phase clock, detect internal quad skew, correct the skew, and output mode register information.
- The memory device has two ranks, each with memory banks and a quad skew adjustment circuit.
- The quad skew adjustment circuits receive a 4-phase clock through first channels.
- The circuits detect internal quad skew of the 4-phase clock.
- The circuits correct the skew of the 4-phase clock based on the detected quad skew.
- The circuits output mode register information corresponding to the detected quad skew through a second channel.
Potential applications of this technology:
- Memory devices in computer systems
- Data storage devices
- High-performance computing systems
Problems solved by this technology:
- Skew in the 4-phase clock can lead to timing errors and data corruption.
- Quad skew adjustment circuits correct the skew, ensuring accurate data storage and retrieval.
Benefits of this technology:
- Improved reliability and accuracy of memory devices.
- Enhanced performance of computer systems and data storage devices.
- Reduction in timing errors and data corruption.
Original Abstract Submitted
A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.
