17839626. DATA STORAGE DEVICE WITH DYNAMIC MAPPING OF LOW-DENSITY PARITY CHECK (LDPC) ENGINES simplified abstract (Western Digital Technologies, Inc.)
DATA STORAGE DEVICE WITH DYNAMIC MAPPING OF LOW-DENSITY PARITY CHECK (LDPC) ENGINES
Organization Name
Western Digital Technologies, Inc.
Inventor(s)
Dattatreya B Nayak of Udupi (IN)
Karthik N E of Chickamagalore (IN)
Noor Mohamed A A of Kumbakonam (IN)
DATA STORAGE DEVICE WITH DYNAMIC MAPPING OF LOW-DENSITY PARITY CHECK (LDPC) ENGINES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17839626 titled 'DATA STORAGE DEVICE WITH DYNAMIC MAPPING OF LOW-DENSITY PARITY CHECK (LDPC) ENGINES
Simplified Explanation
The present patent application addresses the lack of parallelism in a typical approach by introducing a dynamic mapping of low-density parity check (LDPC) engines to flash controllers. This eliminates the static mapping and allows for more efficient processing.
- The patent application introduces a dynamic LDPC mapping to a plurality of flash controllers.
- The approach eliminates the static mapping of LDPC engines, which improves parallelism.
- The devices, methods, and apparatuses described in the patent application aim to address the lack of parallelism in current approaches.
- The innovation allows for more efficient processing of LDPC engines by dynamically mapping them to flash controllers.
Potential Applications
The technology described in this patent application has potential applications in various industries and fields, including:
- Data storage and retrieval systems
- Flash memory controllers
- Error correction systems
- Communication systems
- High-performance computing
Problems Solved
The technology presented in this patent application solves several problems, including:
- Lack of parallelism in current approaches
- Inefficient processing of low-density parity check (LDPC) engines
- Static mapping limitations in flash controllers
- Reduced performance and speed in data storage and retrieval systems
Benefits
The benefits of the technology described in this patent application include:
- Improved parallelism in LDPC processing
- More efficient utilization of flash controllers
- Enhanced performance and speed in data storage and retrieval systems
- Increased reliability and accuracy in error correction systems
- Potential for faster communication systems and high-performance computing
Original Abstract Submitted
The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.
