17837260. SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Hyunsu Kim of Cheonan-si (KR)

SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17837260 titled 'SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Simplified Explanation

The abstract describes a semiconductor package that includes a package substrate, a spacer chip with a groove pattern, at least one semiconductor chip mounted on the package substrate, and a sealing member covering the chips.

  • The package substrate serves as a base for the semiconductor package.
  • The spacer chip is attached to the package substrate and has a groove pattern on its surface.
  • The semiconductor chip(s) are mounted on the spacer chip using an adhesive film.
  • A sealing member is applied on the package substrate, covering both the spacer chip and the semiconductor chip(s).

Potential Applications

  • Electronics industry
  • Semiconductor manufacturing

Problems Solved

  • Provides a structure for mounting semiconductor chips on a package substrate.
  • Ensures proper alignment and spacing between the chips.
  • Protects the chips from external elements.

Benefits

  • Improved packaging efficiency and reliability.
  • Enhanced protection for the semiconductor chips.
  • Simplified manufacturing process.


Original Abstract Submitted

A semiconductor package including: a package substrate; a spacer chip attached on a surface of the package substrate, the spacer chip having a groove pattern in a surface of the spacer chip; at least one semiconductor chip mounted on the package substrate, the at least one semiconductor chip being attached on the surface of the spacer chip via an adhesive film; and a sealing member on the surface of the package substrate, the sealing member covering the spacer chip and the at least one semiconductor chip.