17836936. ADDRESS TRANSLATION PREFETCHING FOR INPUT/OUTPUT DEVICES simplified abstract (Microsoft Technology Licensing, LLC)

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ADDRESS TRANSLATION PREFETCHING FOR INPUT/OUTPUT DEVICES

Organization Name

Microsoft Technology Licensing, LLC

Inventor(s)

Ramakrishna Huggahalli of Scottsdale AZ (US)

Shachar Raindel of Redmond WA (US)

ADDRESS TRANSLATION PREFETCHING FOR INPUT/OUTPUT DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17836936 titled 'ADDRESS TRANSLATION PREFETCHING FOR INPUT/OUTPUT DEVICES

Simplified Explanation

The abstract describes a technology related to input/output memory management unit (IOMMU) in a computing device. Here is a simplified explanation of the abstract:

  • The technology involves an IOMMU in a computing device that receives a prefetch message from a CPU core.
  • The prefetch message includes a virtual address, which is the address used by the CPU core.
  • The IOMMU performs a page walk on the virtual address through a page table stored in the main memory of the computing device.
  • The page walk retrieves a prefetched translation of the virtual address to a physical address, which is the actual location in memory.
  • The prefetched translation is then stored in a translation lookaside buffer (TLB) of the IOMMU.

Potential Applications:

  • This technology can be applied in various computing devices such as servers, personal computers, and mobile devices.
  • It can improve the efficiency of memory management in these devices.

Problems Solved:

  • The technology solves the problem of efficiently translating virtual addresses to physical addresses in a computing device.
  • It reduces the time and resources required for address translation.

Benefits:

  • By prefetching translations, the technology can reduce the latency in accessing memory.
  • It can improve the overall performance and responsiveness of the computing device.
  • The use of a TLB can further enhance the efficiency of address translation.


Original Abstract Submitted

In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.

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