17836453. PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
Organization Name
Inventor(s)
Yongsung Cho of Hwaseong-si (KR)
PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17836453 titled 'PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
Simplified Explanation
The patent application describes a memory device with a memory cell array and a page buffer circuit connected to the memory cell array through multiple bit lines. The page buffer circuit includes multiple page buffers, each with a sensing node.
- The first page buffer in the circuit has a first sensing node that senses data through a first metal wire at a lower metal layer.
- The first page buffer also has a second metal wire connected to the first metal wire at an upper metal layer above the lower metal layer.
- A boost node corresponding to a third metal wire adjacent to the second metal wire is used to control the voltage of the first sensing node, enabling boost-up and boost-down operations.
Potential applications of this technology:
- Memory devices in computers, smartphones, and other electronic devices.
- Solid-state drives (SSDs) and other storage devices.
- High-performance computing systems.
Problems solved by this technology:
- Improved sensing of data in memory devices.
- Enhanced control of voltage levels in memory cells.
- Increased efficiency and reliability of memory operations.
Benefits of this technology:
- Higher data transfer rates and improved overall performance of memory devices.
- More efficient use of power, leading to longer battery life in portable devices.
- Enhanced reliability and durability of memory cells.
Original Abstract Submitted
A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.
