17835292. Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter simplified abstract (APPLE INC.)
Contents
- 1 Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
Organization Name
Inventor(s)
Reetika K Agarwal of Sunnyvale CA (US)
Abbas Komijani of Mountain View CA (US)
Hongrui Wang of San Jose CA (US)
Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter - A simplified explanation of the abstract
This abstract first appeared for US patent application 17835292 titled 'Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
Simplified Explanation
An electronic device is described that includes wireless circuitry with mixer circuitry. The mixer circuitry receives oscillator signals from a partial-fractional phase-locked loop (PLL). The PLL includes a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To enable the partial-fractional capability of the PLL, a bitstream is received by the frequency divider from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator outputs a periodic non-randomized signal, and the finite impulse response filter increases the frequency of toggling of this signal. This configuration reduces phase noise in the partial-fractional PLL.
- The electronic device includes wireless circuitry with mixer circuitry.
- The mixer circuitry receives oscillator signals from a partial-fractional phase-locked loop (PLL).
- The PLL consists of a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop.
- The frequency divider receives a bitstream from a first order sigma delta modulator and a finite impulse response filter.
- The first order sigma delta modulator outputs a periodic non-randomized signal.
- The finite impulse response filter increases the frequency of toggling of the periodic non-randomized signal.
- This configuration reduces phase noise in the partial-fractional PLL.
Potential Applications
This technology can be applied in various electronic devices that require wireless communication capabilities, such as smartphones, tablets, laptops, and IoT devices.
Problems Solved
The technology solves the problem of phase noise in partial-fractional phase-locked loops, which can affect the performance and reliability of wireless communication systems.
Benefits
- Reduced phase noise in the partial-fractional phase-locked loop.
- Improved performance and reliability of wireless communication systems.
- Enhanced signal quality and stability in electronic devices with wireless capabilities.
Original Abstract Submitted
An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
