17832488. INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Meng-Han Wang of Hsinchu City (TW)

Yu-Ting Lin of Hsin-Chu City (TW)

Charlis Lin of Hsinchu County (TW)

Coach Liu of Changhua County (TW)

Wei-Cheng Liu of Hsinchu County (TW)

INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17832488 titled 'INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT CHIPS

Simplified Explanation

The abstract describes an integrated circuit (IC) chip package and a method of fabricating it. The package includes a device layer on one surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the other surface of the substrate. The first interconnect structure includes a fault detection line in a metal line layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line. The fault detection line is connected to the device layer.

• The IC chip package includes a device layer, interconnect structures, and a fault detection line.
• The fault detection line emits a signal indicating the presence or absence of a defect in the device layer.
• The fault detection line is electrically connected to the device layer.
• The package is fabricated using a method that includes forming the device layer, interconnect structures, and fault detection line.

Potential applications of this technology:

• Fault detection in integrated circuit chip packages.
• Quality control in semiconductor manufacturing.
• Monitoring and diagnosing defects in electronic devices.

Problems solved by this technology:

• Detecting defects in the device layer of integrated circuit chip packages.
• Improving quality control in semiconductor manufacturing.
• Enhancing the reliability and performance of electronic devices.

Benefits of this technology:

• Early detection of defects in integrated circuit chip packages.
• Improved manufacturing processes and quality control.
• Enhanced reliability and performance of electronic devices.

Original Abstract Submitted

An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes a device layer on a first surface of a substrate, a first interconnect structure on the device layer, and a second interconnect structure on the second surface of the substrate. The first interconnect structure includes a fault detection line in a first metal line layer and configured to emit an electrical or an optical signal that is indicative of a presence or an absence of a defect in the device layer, a metal-free region on the fault detection line, and a metal line adjacent to the fault detection line in the first metal line layer. The fault detection line is electrically connected to the device layer.