17829669. MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
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MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
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MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17829669 titled 'MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
Simplified Explanation
The abstract describes a memory controller for a semiconductor memory device that includes an access pattern profiler, a row hammer prediction neural network, and a memory interface.
- The access pattern profiler generates a profile of the access pattern of memory cell rows during a specific time interval after they have been refreshed.
- The row hammer prediction neural network uses the access pattern profile to predict the probability of a row hammer occurrence.
- If the predicted probability is equal to or greater than a reference value, the row hammer prediction neural network generates a hammer address, an alert signal, and an outcast row list.
- The memory interface transmits the hammer address, outcast row list, and alert signal to the semiconductor memory device.
Potential applications of this technology:
- Memory controllers in computer systems and electronic devices that use semiconductor memory devices.
- Systems that require reliable and efficient memory access and management.
Problems solved by this technology:
- Row hammer is a phenomenon where repeated accesses to a row of memory cells can cause bit flips in adjacent rows, leading to data corruption and security vulnerabilities.
- This technology helps in predicting and preventing row hammer occurrences, ensuring the reliability and integrity of data stored in the memory device.
Benefits of this technology:
- Improved memory access reliability by detecting and preventing row hammer occurrences.
- Enhanced data integrity and security by reducing the risk of bit flips and data corruption.
- Efficient memory management by profiling access patterns and predicting row hammer probabilities.
Original Abstract Submitted
A memory controller, to control a semiconductor memory device, includes an access pattern profiler, a row hammer prediction neural network, and a memory interface. The access pattern profiler generates an access pattern profile based on a row access pattern on a portion of memory cell rows of the semiconductor memory device during a reference time interval posterior to a refresh interval during which the memory cell rows are refreshed. The row hammer prediction neural network predicts a probability of occurrence based on the access pattern profile. In response to the probability being equal to or greater than a reference value, the row hammer prediction neural network generates a hammer address, an alert signal indicating that the row hammer occurs, and an outcast row list. The memory interface transmits the hammer address, the outcast row list, and the alert signal to the semiconductor memory device.
