17825798. Gate Structure Fabrication Techniques for Reducing Gate Structure Warpage simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
Gate Structure Fabrication Techniques for Reducing Gate Structure Warpage
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chandrashekhar Prakash Savant of Hsinchu (TW)
Kin Shun Chong of Hsinchu City (TW)
Chia-Ming Tsai of Hsinchu County (TW)
Gate Structure Fabrication Techniques for Reducing Gate Structure Warpage - A simplified explanation of the abstract
This abstract first appeared for US patent application 17825798 titled 'Gate Structure Fabrication Techniques for Reducing Gate Structure Warpage
Simplified Explanation
The patent application describes techniques for fabricating gate stacks and gate structures with improved profiles, such as minimal warping and bending and substantially vertical sidewalls. These techniques can be used in various device types.
- Gate fabrication techniques for improved gate stacks and gate structures
- Stress-treated glue layers with reduced residual stress
- Glue layer deposited over a work function layer and treated with ion implantation or annealing
- Glue sublayer/metal layer pairs formed over a work function layer, followed by a poisoning process and another glue sublayer formation
Potential Applications:
- Semiconductor manufacturing
- Integrated circuit fabrication
- Transistor design and production
Problems Solved:
- Warping, bending, bowing, and necking of gate stacks and structures
- Inconsistent gate profiles
- Difficulties in achieving vertical sidewalls
Benefits:
- Improved gate stack and structure profiles
- Enhanced performance and reliability of devices
- Simplified manufacturing processes
Original Abstract Submitted
Gate fabrication techniques are disclosed herein for providing gate stacks and/or gate structures (e.g., high-k/metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and/or substantially vertical sidewalls), which may be implemented in various device types. For example, gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress that is less than about 1.0 gigapascals (GPa) (e.g., about -2.5 GPa to about 0.8 GPa). In some embodiments, a stress-treated glue layer is provided by depositing a glue layer over a work function layer and performing a stress reduction treatment, such as an ion implantation process and/or an annealing process in a gas ambient, on the glue layer. In some embodiments, a stress-treated glue layer is provided by forming at least one glue sublayer/metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair.
