17823711. APPARATUSES AND METHODS FOR PROCESSING SINGLE INSTRUCTION FOR IMAGE TRANSFORMATION FROM NON-INTEGRAL LOCATIONS simplified abstract (QUALCOMM Incorporated)
Contents
- 1 APPARATUSES AND METHODS FOR PROCESSING SINGLE INSTRUCTION FOR IMAGE TRANSFORMATION FROM NON-INTEGRAL LOCATIONS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 APPARATUSES AND METHODS FOR PROCESSING SINGLE INSTRUCTION FOR IMAGE TRANSFORMATION FROM NON-INTEGRAL LOCATIONS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
APPARATUSES AND METHODS FOR PROCESSING SINGLE INSTRUCTION FOR IMAGE TRANSFORMATION FROM NON-INTEGRAL LOCATIONS
Organization Name
Inventor(s)
Venkata Prema Sai Sravan Patchala of Bangalore (IN)
Mithil Ramteke of Bangalore (IN)
Sridhar Kandimalla of Bengalaru (IN)
Himanshu Pradeep Aswani of Pune (IN)
APPARATUSES AND METHODS FOR PROCESSING SINGLE INSTRUCTION FOR IMAGE TRANSFORMATION FROM NON-INTEGRAL LOCATIONS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823711 titled 'APPARATUSES AND METHODS FOR PROCESSING SINGLE INSTRUCTION FOR IMAGE TRANSFORMATION FROM NON-INTEGRAL LOCATIONS
Simplified Explanation
- Processor pipeline circuit for non-integral transformation of an image using a single instruction
- Data fetch circuit fetches pixels of input image
- Weights access circuit determines weights for pixels based on offsets and interpolation type
- Multiply and add circuit calculates output pixel by multiplying input pixels with weights and summing the results
Potential Applications
- Image processing
- Computer vision
- Graphics rendering
Problems Solved
- Efficient non-integral image transformation
- Simplified processing of image data
- Streamlined image manipulation tasks
Benefits
- Faster image transformation
- Reduced processing complexity
- Improved image quality and accuracy
Original Abstract Submitted
A processor pipeline circuit in a processor for non-integral transformation of an image utilizing a single instruction is disclosed. The processor pipeline circuit comprises a data fetch circuit configured to receive a memory address of the input image and fetch a plurality of pixels of the input image. The processor pipeline circuit further comprises a weights access circuit configured to receive an element of the array of offsets and the interpolation type parameter. The weights access circuit is configured to determine weights to be applied to the plurality of pixels of the input image. The processor pipeline circuit further comprises a multiply and add circuit configured to calculate the output pixel of the transformed image by multiplying the plurality of pixels of the input image by the weights and summing each resulting product.
