17822390. CAPACITORLESS DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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CAPACITORLESS DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF FORMATION

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Yun-Feng Kao of New Taipei City (TW)

Chia Yu Ling of Hsinchu City (TW)

Katherine H. Chiang of New Taipei City (TW)

CAPACITORLESS DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF FORMATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17822390 titled 'CAPACITORLESS DYNAMIC RANDOM ACCESS MEMORY AND METHODS OF FORMATION

Simplified Explanation

The capacitorless dynamic random access memory (DRAM) cell described in the patent application includes transistors with a channel layer that has a unique shape, such as an inverted U shape, an ohm symbol (Ω) shape, or an uppercase Omega (Ω) shape. This shape increases the channel length of the transistors, reducing off current and current leakage, which in turn improves data retention and reliability without increasing the footprint of the transistors. Additionally, this shape allows for a top-gate structure, simplifying integration with other transistors in the cell.

  • The DRAM cell includes transistors with a channel layer in a unique shape to increase channel length.
  • The unique shape reduces off current and current leakage, improving data retention and reliability.
  • The shape enables a top-gate structure, simplifying integration with other transistors in the cell.

Potential Applications

  • Memory devices
  • Integrated circuits
  • Consumer electronics

Problems Solved

  • Reduced off current and current leakage
  • Improved data retention and reliability
  • Simplified integration with other transistors

Benefits

  • Increased performance and reliability of DRAM cells
  • Simplified manufacturing process
  • Enhanced data storage capabilities


Original Abstract Submitted

A capacitorless dynamic random access memory (DRAM) cell may include a plurality of transistors. At least a subset of the transistors may include a channel layer that approximately resembles an inverted U shape, an ohm symbol (Ω) shape, or an uppercase/capital omega (Ω) shape. The particular shape of the channel layer provides an increased channel length for the subset of the transistors, which may reduce the off current and may reduce current leakage in the subset of the transistors. The reduced off current and reduced current leakage may increase data retention in the subset of the transistors and/or may increase the reliability of the subset of the transistors without increasing the footprint of the subset of the transistors. Moreover, the particular shape of the channel layer enables the subset of the transistors to be formed with a top-gate structure, which provides low integration complexity with other transistors in the capacitorless DRAM cell.

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