17820995. SEMICONDUCTOR DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Chanho Lee of Hwaseong-si (KR)
Taehyung Kim of Yongin-si (KR)
Sangyeop Baeck of Yongin-si (KR)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17820995 titled 'SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a semiconductor device that includes a substrate with memory cells and a comparator circuit. It also includes true and complementary bit lines, power supply wiring, and word lines.
- The semiconductor device includes a substrate with memory cells and a comparator circuit.
- It has true and complementary bit lines that are connected to the memory cells.
- The device also includes power supply wiring that is connected to the memory cells.
- It has word lines that are connected to the memory cells.
- The device includes a ground pad that is in the same position as the word line pads.
Potential applications of this technology:
- This semiconductor device can be used in various electronic devices such as computers, smartphones, and tablets.
- It can be used in memory modules and storage devices.
Problems solved by this technology:
- The semiconductor device solves the problem of efficiently connecting memory cells and a comparator circuit on a substrate.
- It solves the problem of providing power supply wiring and word lines in a compact and efficient manner.
Benefits of this technology:
- The semiconductor device provides a compact and efficient design for connecting memory cells and a comparator circuit.
- It allows for efficient power supply wiring and word line connections.
- The device can improve the performance and reliability of electronic devices.
Original Abstract Submitted
A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.
