17819482. POWER VIAS FOR BACKSIDE POWER DISTRIBUTION NETWORK simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

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POWER VIAS FOR BACKSIDE POWER DISTRIBUTION NETWORK

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Ching-Yu Huang of Hsinchu City (TW)

Kuan Yu Chen of Hsinchu City (TW)

Shih-Wei Peng of Hsinchu City (TW)

Wei-Cheng Lin of Taichung City (TW)

Jiann-Tyng Tzeng of Hsinchu (TW)

POWER VIAS FOR BACKSIDE POWER DISTRIBUTION NETWORK - A simplified explanation of the abstract

This abstract first appeared for US patent application 17819482 titled 'POWER VIAS FOR BACKSIDE POWER DISTRIBUTION NETWORK

Simplified Explanation

The device described in the patent application includes two rows of active areas and a power via. The first row of active areas has different widths in a certain direction, while the second row of active areas has the same width. The power via connects different layers of the device and is positioned between the two rows of active areas.

  • Two rows of active areas with different widths
  • Power via connecting layers of the device
  • Specific positioning of the power via between the rows of active areas

Potential Applications

  • Semiconductor devices
  • Integrated circuits
  • Electronics manufacturing

Problems Solved

  • Efficient power distribution in devices
  • Improved connectivity between different layers
  • Enhanced performance of semiconductor devices

Benefits

  • Increased efficiency in power distribution
  • Better connectivity between layers
  • Improved overall performance of devices


Original Abstract Submitted

A device includes a first row of active areas, a second row of active areas, and a first power via. The first row of active areas includes first active areas that extend in a first direction and second active areas that extend in the first direction. Each of the first active areas has a first width in a second direction and each of the second active areas has a second width in the second direction that is smaller than the first width. The second row of active areas is situated above or below the first row of active areas and includes third active areas that extend in the first direction. Each of the third active areas has the second width in the second direction. The first power via extends in a third direction between a transistor level of the device and a backside metal layer of the device and is situated between the first row of active areas and the second row of active areas.

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