17818048. MONOLITHIC THREE-DIMENSIONAL (3D) COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHOD OF MANUFACTURE simplified abstract (QUALCOMM Incorporated)
MONOLITHIC THREE-DIMENSIONAL (3D) COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHOD OF MANUFACTURE
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MONOLITHIC THREE-DIMENSIONAL (3D) COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHOD OF MANUFACTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17818048 titled 'MONOLITHIC THREE-DIMENSIONAL (3D) COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHOD OF MANUFACTURE
Simplified Explanation
The abstract describes a monolithic 3D complementary field-effect transistor (CFET) circuit that includes two CFET structures in a logic circuit within a device layer. The circuit also includes a first interconnect layer that provides input and output contacts for the logic circuit. Each CFET structure consists of an upper FET with one type (P-type or N-type) and a lower FET with the opposite type (N-type or P-type). The FETs can be interconnected to form a two-input NOR or NAND circuit. Vertical access interconnects (vias) can be formed within the device layer to connect the FETs externally and to each other. The FETs can be bulk-type transistors or SOI transistors.
- Monolithic 3D CFET circuit with two CFET structures in a logic circuit within a device layer
- First interconnect layer provides input and output contacts for the logic circuit
- CFET structures consist of upper and lower FETs with different types
- FETs can be interconnected to form a two-input NOR or NAND circuit
- Vertical access interconnects (vias) allow external and internal connections between FETs
- FETs can be bulk-type or SOI transistors
Potential applications of this technology:
- Integrated circuits for electronic devices
- Logic circuits for computing systems
- Memory circuits for storage devices
Problems solved by this technology:
- Increased circuit density and performance in a compact design
- Improved interconnectivity between FETs within the device layer
- Enhanced functionality with the ability to form NOR and NAND circuits
Benefits of this technology:
- Higher integration and miniaturization of electronic circuits
- Improved performance and efficiency of logic and memory circuits
- Increased flexibility in circuit design and functionality
Original Abstract Submitted
A monolithic 3D complementary field-effect transistor (FET) (CFET) circuit includes a first CFET structure and a second CFET structure in a logic circuit within a device layer. A first interconnect layer disposed on the device layer provides first and second input contacts and an output contact of a logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs in the monolithic 3D CFET circuit may be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) may be formed within the device layer to interconnect the FETs externally and to each other. The FETs may be formed as bulk-type transistors or SOI transistors.
