17817435. MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES HAVING EFFICIENT UNIT CELL LAYOUTS simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES HAVING EFFICIENT UNIT CELL LAYOUTS

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Jongsun Park of Seoul (KR)

Yunho Jang of Seoul (KR)

Seonggeon Park of Seongnam-si (KR)

MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES HAVING EFFICIENT UNIT CELL LAYOUTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17817435 titled 'MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES HAVING EFFICIENT UNIT CELL LAYOUTS

Simplified Explanation

The patent application describes a semiconductor memory device that utilizes spin-orbit torque (SOT) patterns and magnetic tunnel junction patterns to store and retrieve data.

• The memory cell consists of a spin-orbit torque (SOT) pattern, a magnetic tunnel junction pattern, a read transistor, and a write transistor.
• The SOT pattern is electrically coupled to the source line and extends adjacent to the magnetic tunnel junction pattern.
• The read transistor is connected to the magnetic tunnel junction pattern and the bit line, with its gate terminal connected to the first word line.
• The write transistor is connected to the SOT pattern and the magnetic tunnel junction pattern, with its gate terminal connected to the second word line.

Potential applications of this technology:

• Memory devices in electronic devices such as smartphones, tablets, and computers.
• Data storage in cloud computing and data centers.
• High-speed and low-power memory solutions for artificial intelligence and machine learning applications.

Problems solved by this technology:

• Improves the performance and efficiency of semiconductor memory devices.
• Enables higher density memory storage.
• Reduces power consumption and heat generation.

Benefits of this technology:

• Faster data access and retrieval.
• Increased memory capacity.
• Lower power consumption and improved energy efficiency.

Original Abstract Submitted

A semiconductor memory device includes first and second word lines, a bit line, a source line, and a memory cell. The memory cell includes a spin-orbit torque (SOT) pattern having a first end electrically coupled to the source line, a magnetic tunnel junction pattern extending adjacent the SOT pattern, and a read transistor having a first current carrying terminal electrically coupled to a first end of the magnetic tunnel junction pattern, a second current carrying terminal electrically coupled to the bit line, and a gate terminal electrically coupled to the first word line. The memory cell also includes a write transistor having a first current carrying terminal electrically coupled to a second end of the SOT pattern, a second current carrying terminal electrically coupled to the first end of the magnetic tunnel junction pattern, and a gate terminal electrically coupled to the second word line.