17815775. CLOCK SYNTHESIZER simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
CLOCK SYNTHESIZER
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
CLOCK SYNTHESIZER - A simplified explanation of the abstract
This abstract first appeared for US patent application 17815775 titled 'CLOCK SYNTHESIZER
Simplified Explanation
The abstract of this patent application describes a clock synthesizer that includes a clock buffer, a Duty Cycle Corrector (DCC) circuit, and a current source. The clock buffer stores an input clock signal, while the DCC circuit adjusts the duty cycle of the input clock signal based on a control signal. The output clock signal, which is the duty cycle corrected input clock signal, is generated and provided. The current source is responsible for sinking a clamping current to the DCC circuit.
- The clock synthesizer includes a clock buffer, a DCC circuit, and a current source.
- The clock buffer stores the input clock signal.
- The DCC circuit adjusts the duty cycle of the input clock signal based on a control signal.
- The output clock signal is generated and provided, which is the duty cycle corrected input clock signal.
- The current source sinks a clamping current to the DCC circuit.
Potential applications of this technology:
- Clock synthesis in electronic devices and systems.
- Improving the accuracy and stability of clock signals in various applications, such as data communication, signal processing, and timing circuits.
Problems solved by this technology:
- Inaccurate or unstable clock signals can lead to timing errors and reduced performance in electronic devices and systems.
- Duty cycle correction ensures that the clock signal has the desired ratio of high and low states, improving the reliability and functionality of the system.
Benefits of this technology:
- Provides a reliable and accurate clock signal for various electronic applications.
- Allows for precise control of the duty cycle, ensuring proper timing and synchronization.
- Enhances the overall performance and efficiency of electronic devices and systems.
Original Abstract Submitted
A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.
