17815285. MEMORY STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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MEMORY STRUCTURE

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Jhon-Jhy Liaw of Zhudong Township (TW)

MEMORY STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17815285 titled 'MEMORY STRUCTURE

Simplified Explanation

The abstract describes a memory structure that includes a static random-access memory (SRAM) cell with various transistors and nanostructures stacked vertically. It also includes write bit-line conductors and a write bit-line-bar conductor in a metal layer below the SRAM cell.

  • The SRAM cell has multiple transistors, including pull-up (PU) and pull-down (PD) transistors for write ports, pass-gate (PG) transistors for write ports, PD transistors for read ports, and PG transistors for read ports.
  • The nanostructures are vertically stacked within the transistors.
  • The write bit-line conductor is connected to the source/drain feature of the first write-port pass-gate transistor.
  • The write bit-line-bar conductor is connected to the source/drain feature of the second write-port pass-gate transistor.

Potential applications of this technology:

  • Memory devices: This memory structure can be used in various memory devices, such as computer RAM, cache memory, and embedded memory in electronic devices.
  • Data storage: The SRAM cell can store and retrieve data quickly, making it suitable for applications that require fast access to data, such as real-time processing and high-speed computing.

Problems solved by this technology:

  • Data access speed: The SRAM cell's design and structure allow for faster data access compared to other memory technologies like dynamic random-access memory (DRAM).
  • Data retention: The SRAM cell can retain data without the need for constant refreshing, ensuring data integrity and reducing power consumption.

Benefits of this technology:

  • Faster data processing: The SRAM cell's fast access speed enables quicker data processing, improving overall system performance.
  • Lower power consumption: The SRAM cell's ability to retain data without refreshing reduces power consumption, making it energy-efficient.
  • Compact design: The vertical stacking of nanostructures and the use of metal layers optimize space utilization, allowing for a more compact memory structure.


Original Abstract Submitted

A memory structure includes a static random-access memory (SRAM) cell having a cell boundary. The SRAM cell includes a first write-port pull-up (PU) transistor and a second write-port PU transistor, a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, a second write-port PG transistor, a first read-port PD transistor, a second read-port PD transistor, a first read-port PG transistor, and a second read-port PG transistor respectively including nanostructures that are vertically stacked from each other. The memory structure further includes a write bit-line conductor and a write bit-line-bar conductor in a first metal layer under the SRAM cell, wherein the write bit-line conductor is electrically connected to a source/drain feature of the first write-port pass-gate transistor and the write bit-line-bar conductor is electrically connected to a source/drain feature of the second write-port pass-gate transistor.

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