17808566. COMMON SELF ALIGNED GATE CONTACT FOR STACKED TRANSISTOR STRUCTURES simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
Contents
- 1 COMMON SELF ALIGNED GATE CONTACT FOR STACKED TRANSISTOR STRUCTURES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 COMMON SELF ALIGNED GATE CONTACT FOR STACKED TRANSISTOR STRUCTURES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Abstract
- 1.6 Patent/Innovation
- 1.7 Potential Applications
- 1.8 Problems Solved
- 1.9 Benefits
- 1.10 Original Abstract Submitted
COMMON SELF ALIGNED GATE CONTACT FOR STACKED TRANSISTOR STRUCTURES
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
Xuan Liu of Clifton Park NY (US)
Junli Wang of Slingerlands NY (US)
COMMON SELF ALIGNED GATE CONTACT FOR STACKED TRANSISTOR STRUCTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17808566 titled 'COMMON SELF ALIGNED GATE CONTACT FOR STACKED TRANSISTOR STRUCTURES
Simplified Explanation
Abstract
A stacked semiconductor structure is described in this patent application. The structure consists of a top transistor placed above a bottom transistor, with a single gate contact that is in electrical contact with both the top gate conductor of the top transistor and the bottom gate conductor of the bottom transistor.
Patent/Innovation
- Stacked semiconductor structure with a top transistor and a bottom transistor.
- Single gate contact in electrical contact with both transistors.
- Allows for improved integration and compactness of semiconductor devices.
Potential Applications
This technology has potential applications in various fields, including:
- Integrated circuits
- Microprocessors
- Memory devices
- Power electronics
- Communication devices
Problems Solved
The stacked semiconductor structure solves several problems, such as:
- Limited space for integrating multiple transistors in a compact manner.
- Difficulty in achieving efficient electrical contact between stacked transistors.
- Complex fabrication processes for stacked semiconductor devices.
Benefits
The benefits of this technology include:
- Increased integration density, enabling more functionality in a smaller space.
- Improved electrical contact between stacked transistors, enhancing overall device performance.
- Simplified fabrication processes, reducing manufacturing complexity and cost.
Original Abstract Submitted
A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.
