17808360. SINGLE STACK DUAL CHANNEL GATE-ALL-AROUND NANOSHEET WITH STRAINED PFET AND BOTTOM DIELECTRIC ISOLATION NFET simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

SINGLE STACK DUAL CHANNEL GATE-ALL-AROUND NANOSHEET WITH STRAINED PFET AND BOTTOM DIELECTRIC ISOLATION NFET

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Julien Frougier of Albany NY (US)

Andrew M. Greene of Slingerlands NY (US)

Shogo Mochizuki of Mechanicville NY (US)

Kangguo Cheng of Schenectady NY (US)

Ruilong Xie of Niskayuna NY (US)

Heng Wu of Santa Clara CA (US)

Min Gyu Sung of Latham NY (US)

Liqiao Qin of Albany NY (US)

Gen Tsutsui of Albany NY (US)

SINGLE STACK DUAL CHANNEL GATE-ALL-AROUND NANOSHEET WITH STRAINED PFET AND BOTTOM DIELECTRIC ISOLATION NFET - A simplified explanation of the abstract

This abstract first appeared for US patent application 17808360 titled 'SINGLE STACK DUAL CHANNEL GATE-ALL-AROUND NANOSHEET WITH STRAINED PFET AND BOTTOM DIELECTRIC ISOLATION NFET

Simplified Explanation

The abstract describes a patent application for a new type of nanosheet transistor with two channels, one made of silicon germanium (SiGe) and the other made of silicon (Si). The SiGe channel is strained to enhance its performance, while the Si channel is isolated from the bottom dielectric layer.

• The invention is a single stack dual channel gate-all-around nanosheet transistor.
• It includes a strained PFET (p-type field-effect transistor) with a silicon germanium channel.
• It also includes a bottom dielectric isolation NFET (n-type field-effect transistor) with a silicon channel.
• The PFET and NFET are positioned laterally to each other.
• The silicon channel and the silicon germanium channel are staggered in a vertical direction.

Potential Applications

This technology has potential applications in various electronic devices and systems, including:

• Integrated circuits (ICs) for computers, smartphones, and other electronic devices.
• High-performance processors and memory chips.
• Power-efficient devices for Internet of Things (IoT) applications.
• Advanced sensors and imaging devices.

Problems Solved

The patent addresses several challenges in transistor design and fabrication, including:

• Enhancing the performance of p-type transistors by using strained silicon germanium channels.
• Isolating the n-type transistors from the bottom dielectric layer to prevent leakage and improve efficiency.
• Optimizing the layout and arrangement of the dual-channel transistors to maximize performance and minimize interference.

Benefits

The proposed technology offers several benefits over traditional transistor designs:

• Improved performance and efficiency due to the strained silicon germanium channel in the p-type transistor.
• Enhanced isolation and reduced leakage in the n-type transistor through bottom dielectric isolation.
• Compatibility with existing fabrication processes, allowing for easier integration into current manufacturing workflows.
• Potential for higher transistor density and smaller chip sizes, leading to more compact and powerful electronic devices.

Original Abstract Submitted

Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.