17808124. SUBTRACTIVE SOURCE DRAIN CONTACT FOR STACKED DEVICES simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

SUBTRACTIVE SOURCE DRAIN CONTACT FOR STACKED DEVICES

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Heng Wu of Santa Clara CA (US)

Junli Wang of Slingerlands NY (US)

Ruilong Xie of Niskayuna NY (US)

Albert M. Young of Fishkill NY (US)

Albert M. Chu of Nashua NH (US)

Brent A. Anderson of Jericho VT (US)

Ravikumar Ramachandran of Pleasantville NY (US)

SUBTRACTIVE SOURCE DRAIN CONTACT FOR STACKED DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17808124 titled 'SUBTRACTIVE SOURCE DRAIN CONTACT FOR STACKED DEVICES

Simplified Explanation

The abstract describes a field effect transistor (FET) stack and a method for forming a contact to the lower source drain of the lower FET. The contact is adjacent to a vertical side surface of the lower source drain and has a reverse taper metal stud profile. A silicide layer is formed between the contact and the lower source drain.

• The FET stack includes a lower FET and an upper FET.
• A contact is formed to the lower source drain of the lower FET.
• The contact is adjacent to a vertical side surface of the lower source drain.
• A silicide layer is formed between the contact and the lower source drain.
• The overlap region between the silicide and the contact is smaller than the overlap region between the silicide and the first source drain.

Potential applications of this technology:

• Integrated circuits and semiconductor devices
• Electronics industry
• Computing and communication systems

Problems solved by this technology:

• Improved contact formation to the lower source drain of a lower FET
• Enhanced performance and efficiency of FET stacks

Benefits of this technology:

• Improved electrical conductivity and reliability of the contact
• Increased performance and efficiency of FET stacks
• Enables better integration and miniaturization of electronic devices.

Original Abstract Submitted

A field effect transistor (“FET”) stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.