17806827. DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Hyunsub Rie of Yongin-si (KR)

Eunseok Shin of Seoul (KR)

Youngdon Choi of Seoul (KR)

Junyoung Park of Seoul (KR)

Hyunyoon Cho of Uiwang-si (KR)

Junghwan Choi of Hwaseong-si (KR)

DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17806827 titled 'DELAY CIRCUIT AND CLOCK ERROR CORRECTION DEVICE INCLUDING THE SAME

Simplified Explanation

The patent application describes a delay circuit for a clock signal that includes two signal generators and two inverting circuits.

• The first signal generator generates switching signals based on a delay code to adjust the delay time for both the rising and falling edges of the clock signal.
• The first inverting circuit includes multiple inverters that are selectively turned on in response to the switching signals, allowing for precise adjustment of the delay time.
• The second signal generator generates switching signals based on a duty code to further adjust the delay time for the rising and falling edges of the clock signal.
• The second inverting circuit includes pull-up and pull-down units that are selectively turned on in response to the switching signals, providing additional control over the delay time.

Potential applications of this technology:

• Integrated circuits and microprocessors that require precise timing control.
• Communication systems that rely on accurate clock signals.
• High-speed data transmission systems that need to synchronize data streams.

Problems solved by this technology:

• Provides a flexible and precise method for adjusting the delay time of clock signals.
• Allows for fine-tuning of the timing in integrated circuits and communication systems.
• Helps to reduce signal distortion and improve overall system performance.

Benefits of this technology:

• Enables more accurate and reliable operation of electronic devices.
• Reduces the risk of timing errors and signal degradation.
• Enhances the efficiency and performance of integrated circuits and communication systems.

Original Abstract Submitted

A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.