17806660. 3D Embedded Redistribution Layers for IC Substrate Packaging simplified abstract (APPLE INC.)
3D Embedded Redistribution Layers for IC Substrate Packaging
Organization Name
Inventor(s)
Jun Chung Hsu of Cupertino CA (US)
3D Embedded Redistribution Layers for IC Substrate Packaging - A simplified explanation of the abstract
This abstract first appeared for US patent application 17806660 titled '3D Embedded Redistribution Layers for IC Substrate Packaging
Simplified Explanation
The patent application describes improved redistribution layer structures for integrated circuit or system-on-chip packages. These structures allow for self-alignment of via landing pads and via interconnects, resulting in decreased widths or diameters of pads terminating non-stacked vias without requiring extra capture space. The vias in the redistribution layers have vertical or near vertical sidewalls and can have various shapes, widths, or lengths. The traces in the redistribution layers can also have various lengths and shapes, with some extending into layers routing the vias to increase metal density in the traces.
- Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads.
- This self-alignment allows for decreased widths or diameters of pads terminating non-stacked vias without extra capture space.
- The vias in the redistribution layers have vertical or near vertical sidewalls.
- Vias can have various shapes, widths, or lengths.
- Traces in the redistribution layers have various lengths and shapes, with some extending into layers routing the vias to increase metal density in the traces.
Potential Applications
- Integrated circuit packages
- System-on-chip packages
Problems Solved
- Decreased widths or diameters of pads terminating non-stacked vias without extra capture space
- Increased metal density in traces
Benefits
- Improved redistribution layer structures
- Self-alignment of via landing pads and via interconnects
- Increased metal density in traces
Original Abstract Submitted
Improved redistribution layer structures for integrated circuit or system-on-chip (SoC) packages substrate are disclosed. Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads. This self-alignment may allow pads that terminate non-stacked vias to have decreased widths or diameters without extra capture space. The redistribution layers have vias with vertical or near vertical sidewalls. Vias may also have various shapes, widths, or lengths. Traces in the redistribution layers may have various lengths and shapes with lengths that may extend into layers routing the vias to provide increased metal density in the traces.
