17806291. ACCESS OPTIMIZED PARTIAL CACHE COLLAPSE simplified abstract (QUALCOMM Incorporated)

From WikiPatents
Jump to navigation Jump to search

ACCESS OPTIMIZED PARTIAL CACHE COLLAPSE

Organization Name

QUALCOMM Incorporated

Inventor(s)

Hithesh Hassan Lepaksha of Hyderabad (IN)

Sharath Kumar Nagilla of Hyderabad (IN)

Darshan Kumar Nandanwar of Bangalore (IN)

Nirav Narendra Desai of Hyderabad (IN)

Venkata Biswanath Devarasetty of Hyderabad (IN)

ACCESS OPTIMIZED PARTIAL CACHE COLLAPSE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17806291 titled 'ACCESS OPTIMIZED PARTIAL CACHE COLLAPSE

Simplified Explanation

The present disclosure is about systems and methods for improving the performance of a partial cache collapse by a processing device. The method involves counting the number of dirty cache lines in each cache way of a group of cache ways. Dirty cache lines are cache lines that have been modified. Based on the count of dirty cache lines, at least one cache way is selected from the group for collapse. The partial cache collapse procedure is then performed using the selected cache way(s).

  • The method counts the number of modified cache lines in each cache way.
  • At least one cache way is selected for collapse based on the count of modified cache lines.
  • The partial cache collapse procedure is performed using the selected cache way(s).

Potential applications of this technology:

  • Improving the performance of processing devices that utilize cache memory.
  • Enhancing the efficiency of cache management in computer systems.
  • Optimizing the utilization of cache memory in high-performance computing.

Problems solved by this technology:

  • Inefficient cache management can lead to reduced performance in processing devices.
  • Dirty cache lines can occupy valuable cache space, impacting overall system performance.
  • Manual cache management can be time-consuming and error-prone.

Benefits of this technology:

  • Improved performance of processing devices by optimizing cache utilization.
  • Efficient management of dirty cache lines, freeing up cache space for other data.
  • Automated cache collapse procedure reduces the need for manual intervention.


Original Abstract Submitted

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.