17805090. MULTI-LEVEL CELLS, AND RELATED ARRAYS, DEVICES, SYSTEMS, AND METHODS simplified abstract (Micron Technology, Inc.)
Contents
MULTI-LEVEL CELLS, AND RELATED ARRAYS, DEVICES, SYSTEMS, AND METHODS
Organization Name
Inventor(s)
MULTI-LEVEL CELLS, AND RELATED ARRAYS, DEVICES, SYSTEMS, AND METHODS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17805090 titled 'MULTI-LEVEL CELLS, AND RELATED ARRAYS, DEVICES, SYSTEMS, AND METHODS
Simplified Explanation
The patent application describes multi-level cells and related methods, arrays, devices, and systems. It specifically focuses on a memory device that includes a memory array with different sections and digit lines. Here is a simplified explanation of the abstract:
- The memory device has a memory array with multiple sections.
- The first reference section has a certain number of memory cells and a reference digit line.
- The second reference section also has a certain number of memory cells and a reference digit line.
- The target section includes a memory cell and a first digit line connected to the memory cell through a first switch.
- The first digit line is also connected to the first reference digit line through a first sense amplifier.
- The target section also includes a second digit line connected to the first digit line through a second switch.
- The second digit line is further connected to the second reference digit line through a second sense amplifier.
Potential applications of this technology:
- Memory devices in various electronic devices such as smartphones, computers, and tablets.
- Data storage systems in cloud computing and data centers.
- Solid-state drives (SSDs) and other storage devices.
Problems solved by this technology:
- Increase in memory capacity and density by utilizing multi-level cells.
- Improved performance and reliability of memory devices.
- Efficient use of digit lines and sense amplifiers for data retrieval.
Benefits of this technology:
- Higher memory capacity and storage density in a compact device.
- Faster data retrieval and improved overall performance.
- Enhanced reliability and durability of memory devices.
- Cost-effective production and utilization of memory arrays.
Original Abstract Submitted
Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.