17804397. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
KYUNGSOO Kim of Hwaseong-si (KR)
JINYOUNG Park of Anyang-si (KR)
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17804397 titled 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor device that includes various patterns and interconnection lines on a substrate. It specifically focuses on the structure and arrangement of the gate electrode and active contact.
- The semiconductor device includes an active pattern, source/drain pattern, gate electrode, active contact, and interconnection lines.
- The gate electrode has an electrode body portion and a protruding portion that contacts the second lower interconnection line.
- The active contact has a contact body portion and a protruding portion that contacts the first lower interconnection line.
- The device also includes spacers between the gate electrode and active contact, with the first spacer being higher than the second spacer.
Potential applications of this technology:
- Semiconductor manufacturing industry
- Electronics industry
- Integrated circuit design and production
Problems solved by this technology:
- Provides a specific structure and arrangement for the gate electrode and active contact in a semiconductor device.
- Ensures proper contact and connection between the various patterns and interconnection lines.
- Helps improve the performance and reliability of the semiconductor device.
Benefits of this technology:
- Enhanced functionality and efficiency of the semiconductor device.
- Improved electrical conductivity and signal transmission.
- Increased reliability and durability of the device.
Original Abstract Submitted
A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a gate electrode on a channel pattern connected to the source/drain pattern, an active contact on the source/drain pattern, a first lower interconnection line on the active contact, a second lower interconnection line on the gate electrode, a first spacer between the gate electrode and the active contact, and a second spacer between the first spacer and the gate electrode or the active contact. The gate electrode includes an electrode body portion and an electrode protruding portion protruding from a top surface thereof and contacting the second lower interconnection line. The active contact includes a contact body portion and a contact protruding portion protruding from a top surface thereof and contacting the first lower interconnection line. A top surface of the first spacer is higher than a top surface of the second spacer.