17748441. SEMICONDUCTOR MEMORY DEVICE WITH DEFECT DETECTION CAPABILITY simplified abstract (Samsung Electronics Co., Ltd.)

SEMICONDUCTOR MEMORY DEVICE WITH DEFECT DETECTION CAPABILITY

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Seongkyung Kim of Hwaseong-si (KR)

Dahye Min of Suwon-si (KR)

Ukjin Jung of Hwaseong-si (KR)

SEMICONDUCTOR MEMORY DEVICE WITH DEFECT DETECTION CAPABILITY - A simplified explanation of the abstract

This abstract first appeared for US patent application 17748441 titled 'SEMICONDUCTOR MEMORY DEVICE WITH DEFECT DETECTION CAPABILITY

Simplified Explanation

The patent application describes a semiconductor memory device that includes a memory cell region and a test region on a substrate. It includes various components such as an active pattern, a source/drain pattern, a dummy pattern, a first gate electrode, a first common contact, and a first wiring layer.

• The memory device has a separate test region for testing purposes.
• It includes an active pattern and a source/drain pattern for memory cell operation.
• A dummy pattern is present in the test region to simulate the memory cell region.
• A first gate electrode is placed on the dummy pattern for testing purposes.
• The first common contact connects the dummy pattern and the first gate electrode.
• The first wiring layer includes a test line that is connected to the first common contact.
• The active pattern is positioned lower than the dummy pattern.

Potential applications of this technology:

• Semiconductor memory devices used in various electronic devices such as computers, smartphones, and tablets.
• Testing and quality control of semiconductor memory devices during manufacturing.

Problems solved by this technology:

• Provides a separate test region for efficient testing and quality control of the memory device.
• Allows for accurate simulation of the memory cell region using the dummy pattern in the test region.
• Ensures proper electrical connections between the dummy pattern, first gate electrode, and the first wiring layer.

Benefits of this technology:

• Improved testing efficiency and accuracy in semiconductor memory device manufacturing.
• Enhanced quality control measures for ensuring reliable and high-performance memory devices.
• Simplified design and manufacturing process for semiconductor memory devices.

Original Abstract Submitted

According to various embodiments, a semiconductor memory device includes a substrate that includes a memory cell region and a test region. The semiconductor memory device further includes an active pattern on the memory cell region, a source/drain pattern on the active pattern, a dummy pattern on the test region, a first gate electrode on the dummy pattern, a first common contact, and a first wiring layer. The first wiring layer includes a first test line electrically connected to the first common contact. The first common contact includes a first contact pattern in contact with the dummy pattern, and a first gate contact connected to the first gate electrode. The first gate contact includes a body and a protrusion part. A lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.