17746729. Unlimited Bandwidth Shifting Systems and Methods of an All-Digital Phase Locked Loop simplified abstract (APPLE INC.)
Unlimited Bandwidth Shifting Systems and Methods of an All-Digital Phase Locked Loop
Organization Name
Inventor(s)
Ahmed I. Hussein of San Jose CA (US)
Unlimited Bandwidth Shifting Systems and Methods of an All-Digital Phase Locked Loop - A simplified explanation of the abstract
This abstract first appeared for US patent application 17746729 titled 'Unlimited Bandwidth Shifting Systems and Methods of an All-Digital Phase Locked Loop
Simplified Explanation
The patent application is about systems and methods that improve the bandwidth shifting operations of an ADPLL (All-Digital Phase-Locked Loop) without losing lock and allowing unlimited changes in bandwidth.
- The processor can transmit amplification parameters to the ADPLL to implement a bandwidth shift.
- The shift can be triggered by an enable signal, such as a gear trigger control signal or an enable signal generated for aligning with a clock signal.
- These systems and methods enable multiple bandwidth changing operations without increasing the complexity and footprint of the system.
Potential Applications
- Communication systems
- Wireless networks
- Signal processing systems
Problems Solved
- Loss of lock during bandwidth shifting operations
- Limited number of bandwidth changes
- Increased complexity and footprint of the system
Benefits
- Improved bandwidth shifting operations
- Unlimited changes in bandwidth
- No loss of lock
- Reduced complexity and footprint of the system
Original Abstract Submitted
This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.
