17735542. MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Hijung Kim of Suwon-si (KR)

Hoyoun Kim of Suwon-si (KR)

Jungmin You of Hwaseong-si (KR)

Seongjin Cho of Hwaseong-si (KR)

MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17735542 titled 'MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF

Simplified Explanation

The patent application describes a memory device that includes a memory cell array, a target row refresh logic circuit, a victim point table, and a victim point accumulator.

• The memory cell array consists of multiple memory cells connected to wordlines and bitlines.
• The target row refresh logic circuit selects a refresh row address based on victim point values and performs a refresh operation on specific memory cells.
• The victim point table stores the victim point values for different target row addresses.
• The victim point accumulator receives a row address from an external device and calculates a victim point value for corresponding target row addresses during a specific time period.

Potential applications of this technology:

• Memory devices in computers, smartphones, and other electronic devices.
• Data storage systems in cloud computing and data centers.
• Embedded systems in automotive, aerospace, and industrial applications.

Problems solved by this technology:

• Refreshing memory cells to prevent data loss or corruption.
• Efficiently selecting the most critical memory cells for refresh operation.
• Optimizing memory performance and reliability.

Benefits of this technology:

• Improved memory reliability by selectively refreshing critical memory cells.
• Enhanced memory performance by reducing unnecessary refresh operations.
• Cost-effective solution for memory devices with limited resources.

Original Abstract Submitted

A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.