17734700. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
TAEHWAN Kim of HWASEONG-SI (KR)
YOUNG-DEUK Kim of HWASEONG-SI (KR)
KYUNG SUK Oh of SEONGNAM-SI (KR)
EUNGCHANG Lee of HANAM-SI (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17734700 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes vertically-stacked semiconductor chips and connection terminals. Each chip has a substrate, an interconnection layer, penetration electrodes, and groups on the interconnection layer. The interconnection layer consists of an insulating layer and metal layers. The first and second groups are in contact with the second metal layer, while the third group is spaced apart. The first and third groups have pads connected to corresponding connection terminals in a many-to-one manner, and the second group has pads connected to the second connection terminal in a one-to-one manner.
- Vertically-stacked semiconductor chips with connection terminals
- Each chip has a substrate, interconnection layer, penetration electrodes, and groups
- Interconnection layer consists of insulating layer and metal layers
- First and second groups are in contact with second metal layer, third group is spaced apart
- First and third groups have pads connected to corresponding connection terminals in a many-to-one manner
- Second group has pads connected to second connection terminal in a one-to-one manner
Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
Problems Solved
- Efficiently connecting vertically-stacked semiconductor chips
- Simplifying the connection process
- Improving overall performance and reliability of semiconductor packages
Benefits
- Enhanced connectivity between semiconductor chips
- Increased efficiency in manufacturing and assembly processes
- Improved performance and reliability of semiconductor packages
Original Abstract Submitted
A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.
