17731994. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
Seongjin Cho of Hwaseong-si (KR)
Jungmin You of Hwaseong-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17731994 titled 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE
Simplified Explanation
The patent application describes a semiconductor memory device that includes a memory cell array, a row hammer management circuit, a repair control circuit, and a connection logic.
- The memory cell array consists of memory cell rows, each containing volatile memory cells.
- The row hammer management circuit keeps track of access addresses associated with the memory cell rows and stores counting values.
- Based on the counting values, the row hammer management circuit identifies a memory cell row that is being accessed frequently, known as the hammer address.
- The repair control circuit includes repair controllers, each having a defective address storage, and is responsible for repairing any defective memory cell rows.
- The connection logic connects unused repair controllers to the row hammer management circuit, allowing them to be used as a storage resource for a portion of the access addresses.
Potential applications of this technology:
- Semiconductor memory devices used in various electronic devices such as computers, smartphones, and tablets.
- Memory-intensive applications that require efficient management of memory cell access.
Problems solved by this technology:
- Row hammering, which refers to the phenomenon where repeated accesses to a specific memory cell row can cause bit flips in neighboring memory cells.
- Efficient repair of defective memory cell rows without the need for additional resources.
Benefits of this technology:
- Improved reliability and performance of semiconductor memory devices by mitigating the effects of row hammering.
- Cost-effective repair of defective memory cell rows using unused repair controllers.
- Enhanced memory cell array management by dynamically allocating storage resources based on access patterns.
Original Abstract Submitted
A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.
