17725993. MEMORY DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Kyongsik Yeom of Suwon-si (KR)
Changmin Jeon of Yongin-si (KR)
Yongkyu Lee of Gwacheon-si (KR)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17725993 titled 'MEMORY DEVICE
Simplified Explanation
The abstract describes a memory device that includes various components such as a first bit line, memory cell transistor, selection transistor, and a second bit line. The key feature is that the operating voltages of the memory cell transistor and selection transistor are approximately equal.
- The memory device consists of a first bit line, a memory cell transistor, a selection transistor, and a second bit line.
- The first bit line supplies a bias voltage, while the memory cell transistor operates at a specific voltage level.
- The selection transistor controls the supply of the bias voltage to the memory cell transistor.
- The second bit line is connected to the memory cell transistor's drain.
- The operating voltage of the memory cell transistor is approximately equal to the operating voltage of the selection transistor.
Potential applications of this technology:
- Memory devices in various electronic devices such as computers, smartphones, and tablets.
- Storage systems in data centers and servers.
- Embedded memory in microcontrollers and other integrated circuits.
Problems solved by this technology:
- Ensures proper functioning of the memory device by maintaining equal operating voltages.
- Improves the reliability and stability of the memory device.
- Reduces the risk of voltage mismatch and potential damage to the components.
Benefits of this technology:
- Enhanced performance and efficiency of memory devices.
- Increased data storage capacity and speed.
- Improved reliability and durability of memory devices.
- Cost-effective solution for memory technology.
Original Abstract Submitted
A memory device includes a first bit line configured to supply a first bit line bias voltage, a memory cell transistor having a first operating voltage, a selection transistor having a second operating voltage and configured to control the supply of the first bit line bias voltage to a source of the memory cell transistor, and a second bit line connected to a drain of the memory cell transistor. A level of the first operating voltage is about equal to a level of the second operating voltage.
