17725750. IMAGE SENSOR simplified abstract (Samsung Electronics Co., Ltd.)
Contents
IMAGE SENSOR
Organization Name
Inventor(s)
Min-Jun Choi of Hwaseong-si (KR)
Won Oh Ryu of Hwaseong-si (KR)
Hyeon Woo Lee of Hwaseong-si (KR)
IMAGE SENSOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 17725750 titled 'IMAGE SENSOR
Simplified Explanation
The patent application describes an image sensor consisting of two chips. The first chip includes a semiconductor substrate, a photoelectric conversion layer, a color filter, a micro lens, a transistor, an insulating layer, and a metal layer. The second chip includes an insulating layer, a semiconductor substrate, a transistor, a metal layer, a landing metal layer, and a through via.
- The image sensor consists of two chips, each with specific components and layers.
- The first chip has a photoelectric conversion layer, color filter, micro lens, transistor, insulating layer, and metal layer.
- The second chip has a transistor, metal layer, landing metal layer, and through via.
- The through via is a vertical connection passing through the second semiconductor substrate.
- The width of the through via narrows as it approaches the third surface.
Potential Applications
- Digital cameras
- Smartphone cameras
- Surveillance cameras
- Medical imaging devices
Problems Solved
- Improved image sensor design
- Enhanced image quality
- Efficient vertical connections
Benefits
- Higher resolution images
- Improved color accuracy
- Compact and efficient design
- Enhanced performance in various applications
Original Abstract Submitted
An image sensor comprises a first and second chips. The first chip includes a first semiconductor substrate, a photoelectric conversion layer in the first semiconductor substrate, a color filter, a micro lens, a first transistor adjacent to the photoelectric conversion layer, a first insulating layer, and a first metal layer in the first insulating layer and connected to the first transistor. The second chip includes a second insulating layer, a second semiconductor substrate, a second transistor on the second semiconductor substrate, a second metal layer in the second insulating layer and connected to a gate structure of the second transistor through a gate contact, a landing metal layer below the second metal layer, and a through via in direct contact with the landing metal layer and vertically passing through the second semiconductor substrate. A width of the through via becomes narrower as the width approaches the third surface.
