17725300. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Shih-Ming Chang of Hsinchu (TW)

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17725300 titled 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The patent application describes a method of manufacturing a semiconductor device. Here is a simplified explanation of the abstract:

• A first conductive pattern is formed in a layer called the first interlayer dielectric (ILD) layer, which is placed over a substrate.
• A second ILD layer is formed over the first conductive pattern and the first ILD layer.
• A via contact is created in the second ILD layer to connect with the upper surface of the first conductive pattern.
• A second conductive pattern is formed over the via contact, exposing a part of the via contact's upper surface.
• Using the second conductive pattern as a mask, a portion of the via contact is etched, creating a space between the via contact and the second ILD layer.
• Finally, a third ILD layer is formed over the second ILD layer.

Potential applications of this technology:

• Manufacturing of semiconductor devices such as integrated circuits and microprocessors.
• Production of electronic components used in various electronic devices like smartphones, computers, and automotive systems.

Problems solved by this technology:

• Provides a method for creating a space between a via contact and an ILD layer, which can help reduce electrical interference and improve device performance.
• Enables the formation of multiple conductive patterns and layers in a semiconductor device, allowing for more complex circuitry and functionality.

Benefits of this technology:

• Improved electrical performance and reliability of semiconductor devices.
• Increased design flexibility and capability to create more intricate circuitry.
• Enhanced integration of multiple components in a smaller footprint, leading to miniaturization and improved efficiency of electronic devices.

Original Abstract Submitted

In a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive pattern and the first ILD layer, a via contact is formed in the second ILD layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer, and a third ILD layer is formed over the second ILD layer.