17724942. MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME
Organization Name
Inventor(s)
Jungmin You of Hwaseong-si (KR)
Seongjin Cho of Hwaseong-si (KR)
MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17724942 titled 'MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND METHOD OF OPERATING THE SAME
Simplified Explanation
The patent application describes a memory device that includes a memory cell array, a target row refresh logic, a weak pattern detector, and a mode register circuit.
- The memory cell array has multiple memory cells connected to wordlines and bitlines.
- The target row refresh logic performs a refresh operation on specific rows of the memory cell array in response to a refresh management mode command.
- The weak pattern detector is activated based on a register update bit value in the refresh management mode command and provides a risk level for each of the target rows.
- The mode register circuit updates at least one mode register value based on the risk level.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Data storage systems in servers and data centers.
- Embedded memory in various electronic devices.
Problems solved by this technology:
- Memory cells can degrade over time, leading to data corruption or loss.
- Refreshing memory cells periodically helps to maintain data integrity.
- However, refreshing all memory cells can be inefficient and time-consuming.
- This technology provides a targeted approach to refresh only specific rows that are at a higher risk of degradation.
Benefits of this technology:
- Improved memory cell refresh efficiency by selectively refreshing only target rows.
- Reduced power consumption by avoiding unnecessary refresh operations.
- Enhanced data integrity and reliability by addressing potential weak patterns in memory cells.
Original Abstract Submitted
A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.
