17723747. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Hyeon-Woo Jang of Hwaseong-si (KR)
Dong-Wan Kim of Hwaseong-si (KR)
Dong-sik Park of Suwon-si (KR)
Jihoon Chang of Yongin-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17723747 titled 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes a method for fabricating semiconductor memory devices. Here are the key points:
- The method involves providing a substrate with a cell array region and a boundary region.
- A device isolation layer is formed on the cell array region to define active sections.
- An intermediate layer is formed on the boundary region of the substrate.
- An electrode layer is then formed on the substrate, covering the intermediate layer on the boundary region.
- A capping layer is formed on top of the electrode layer.
- An additional capping pattern is created on the boundary region, which includes a step difference to the capping layer.
- An etching process is performed on the additional capping pattern, capping layer, and electrode layer to form bit lines that run across the active sections.
- The etching process exposes the electrode layer simultaneously on the cell array region and the boundary region.
Potential applications of this technology:
- This method can be used in the fabrication of semiconductor memory devices, such as flash memory or DRAM.
- It can improve the efficiency and performance of memory devices by enabling the formation of bit lines that run across active sections.
Problems solved by this technology:
- The method solves the problem of forming bit lines that run across active sections on a substrate with a cell array region and a boundary region.
- It addresses the challenge of simultaneously exposing the electrode layer during the etching process on both the cell array region and the boundary region.
Benefits of this technology:
- The method allows for the efficient fabrication of semiconductor memory devices.
- It enables the formation of bit lines that can improve the performance and functionality of memory devices.
- The simultaneous exposure of the electrode layer on both the cell array region and the boundary region simplifies the fabrication process.
Original Abstract Submitted
Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.
