17719622. METHOD OF FORMING A WIRING AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
METHOD OF FORMING A WIRING AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
Organization Name
Inventor(s)
Hyunchul Lee of Hwaseong-si (KR)
Kijeong Kim of Hwaseong-si (KR)
Donghwi Shin of Yongin-si (KR)
Hyunsil Hong of Hwaseong-si (KR)
METHOD OF FORMING A WIRING AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17719622 titled 'METHOD OF FORMING A WIRING AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
Simplified Explanation
The abstract describes a method for forming a wiring structure on a substrate using a low-k dielectric material. The process involves several steps, including etching, forming protective patterns, and removing masks and patterns.
- The method involves forming an insulating interlayer on a substrate.
- A first etching mask is then formed on the insulating interlayer.
- A first etching process is performed to create an opening through the insulating interlayer.
- The first etching mask is removed.
- A protection pattern is formed on the bottom and sides of the first opening.
- A second etching mask is formed on the protection pattern and the insulating interlayer.
- A second etching process is performed to create a second opening through the insulating interlayer.
- The second etching mask is removed.
- The protection pattern is removed.
- Finally, a wiring structure is formed in each of the first and second openings.
Potential Applications
- Semiconductor manufacturing
- Integrated circuit fabrication
- Electronics industry
Problems Solved
- Formation of wiring structures on a substrate
- Protection of the insulating interlayer during etching processes
Benefits
- Improved efficiency in forming wiring structures
- Enhanced protection of the insulating interlayer
- Potential for higher performance and reliability of electronic devices
Original Abstract Submitted
In a method of forming a wiring, an insulating interlayer including a low-k dielectric material is formed on a substrate. A first etching mask is formed on the insulating interlayer. A first etching process is performed using the first etching mask to form a first opening through the insulating interlayer. The first etching mask is removed. A protection pattern is formed on a bottom and a side of the first opening. A second etching mask is formed on the protection pattern and the insulating interlayer. A second etching process is performed using a second etching mask to form a second opening through the insulating interlayer. The second etching mask is removed. The protection pattern is removed. A wiring is formed in each of the first and second openings.
