17706191. APPARATUS AND METHOD FOR IN-PHASE AND QUADRATURE PHASE (IQ) GENERATION simplified abstract (Samsung Electronics Co., Ltd.)
Contents
APPARATUS AND METHOD FOR IN-PHASE AND QUADRATURE PHASE (IQ) GENERATION
Organization Name
Inventor(s)
VISHNU Kalyanamahadevi Gopalan Jawarlal of BANGALORE (IN)
SUMANTH Chakkirala of BANGALORE (IN)
APPARATUS AND METHOD FOR IN-PHASE AND QUADRATURE PHASE (IQ) GENERATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17706191 titled 'APPARATUS AND METHOD FOR IN-PHASE AND QUADRATURE PHASE (IQ) GENERATION
Simplified Explanation
The patent application describes an apparatus for generating in-phase and quadrature phase signals using a clock input. It includes a clock distributor, two IQ divider circuits, a clock processing circuit, and a multiplexer circuit.
- The apparatus uses a CMOS clock distributor to provide a clock input.
- A first IQ divider circuit divides the clock input into in-phase and quadrature phase signals.
- A clock processing circuit processes the clock input.
- A second IQ divider circuit divides the processed clock input into in-phase and quadrature phase signals.
- A multiplexer circuit selects the output from either the first or second IQ divider circuit.
Potential applications of this technology:
- Wireless communication systems
- Radar systems
- Satellite communication systems
- Software-defined radios
Problems solved by this technology:
- Efficient generation of in-phase and quadrature phase signals
- Simplified circuit design
- Improved signal processing capabilities
Benefits of this technology:
- Higher accuracy in signal generation
- Reduced power consumption
- Increased flexibility in signal processing
Original Abstract Submitted
An apparatus for in-phase and quadrature phase (“IQ”) generation comprises a CMOS clock distributor for providing a clock input. A first IQ divider circuit is configured for receiving the clock input and dividing the clock input into in-phase and quadrature phase (IQ) output. A clock processing circuit is configured for processing the clock input. A second IQ divider circuit is configured for receiving the processed clock input and dividing the processed clock input into in-phase and quadrature phase (IQ) output. A multiplexer circuit is coupled to the first IQ divider circuit and the second IQ divider circuit for selecting the IQ output from the first IQ divider circuit or the second IQ divider circuit.
