17703329. Transistor Gate Structures and Methods of Forming the Same simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

Transistor Gate Structures and Methods of Forming the Same

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Hsueh-Ju Chen of Taipei City (TW)

Yi Hsuan Chen of Hsinchu (TW)

Jyun-Yi Wu of Hsinchu (TW)

Wen-Hung Huang of Hsinchu (TW)

Tsung-Da Lin of Pingtung County (TW)

Jian-Hao Chen of Hsinchu (TW)

Cheng-Lung Hung of Hsinchu (TW)

Kuo-Feng Yu of Zhudong Township (TW)

Transistor Gate Structures and Methods of Forming the Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 17703329 titled 'Transistor Gate Structures and Methods of Forming the Same

Simplified Explanation

The patent application describes a device that includes a substrate with an isolation region, and two semiconductor fins protruding above the isolation region. Each semiconductor fin has a gate dielectric layer consisting of an interfacial layer and a high-k dielectric layer.

• The first channel region of the first semiconductor fin has a thicker interfacial layer compared to the second channel region of the second semiconductor fin.
• The second channel region of the second semiconductor fin has a greater height than the first channel region of the first semiconductor fin.

Potential applications of this technology:

• Integrated circuits
• Transistors
• Semiconductor devices

Problems solved by this technology:

• Improved performance and efficiency of semiconductor devices
• Enhanced control over the flow of electrical current

Benefits of this technology:

• Higher speed and lower power consumption in electronic devices
• Improved reliability and stability of integrated circuits
• Enables the development of smaller and more compact devices.

Original Abstract Submitted

In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a first gate dielectric on a first channel region of the first semiconductor fin, the first gate dielectric including a first interfacial layer and a first high-k dielectric layer; a second semiconductor fin protruding above the isolation region; and a second gate dielectric on a second channel region of the second semiconductor fin, the second gate dielectric including a second interfacial layer and a second high-k dielectric layer, a first portion of the first interfacial layer on the first channel region having a greater thickness than a second portion of the second interfacial layer on the second channel region, the second channel region having a greater height than the first channel region.