17703049. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Sungyong Cho of Anyang-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17703049 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Simplified Explanation
The patent application describes a semiconductor memory device that includes a memory cell array, a row hammer management circuit, and a refresh control circuit.
- The memory cell array consists of multiple memory cell rows.
- The row hammer management circuit keeps track of the number of times each memory cell row is accessed and stores this information as count data.
- When a memory cell row is accessed more than a predetermined reference number of times, the row hammer management circuit identifies it as a "hammer address".
- An internal read-update-write operation is performed on the hammer address to prevent data corruption.
- The refresh control circuit receives the hammer address and performs a hammer refresh operation on the adjacent memory cell rows to prevent data loss.
Potential applications of this technology:
- Semiconductor memory devices used in various electronic devices such as computers, smartphones, and tablets.
- Memory-intensive applications that require efficient memory management and data integrity.
Problems solved by this technology:
- Row hammer is a phenomenon where repeated accesses to a memory cell row can cause bit flips in adjacent rows, leading to data corruption and loss.
- This technology addresses the row hammer problem by identifying intensively accessed memory cell rows and performing necessary operations to prevent data corruption and loss.
Benefits of this technology:
- Improved data integrity by preventing data corruption and loss caused by row hammer.
- Efficient memory management by identifying and addressing intensively accessed memory cell rows.
- Enhanced reliability and performance of semiconductor memory devices.
Original Abstract Submitted
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.
