17700818. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Yeonho Jang of Cheonan-si (KR)
Shang-Hoon Seo of Suwon-si (KR)
Jaegwon Jang of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17700818 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes semiconductor packages and their fabrication methods. These packages consist of a lower structure and an upper redistribution layer. The lower structure includes various layers such as a bump layer, redistribution layer, semiconductor chip, molding layer, conductive pillar, and under pad layer. The upper redistribution layer includes additional layers such as a bump layer and redistribution layers.
- The first redistribution layer in the lower structure has a pattern that includes a line part and a via part. The width of the via part increases towards the line part from the bottom surface of the via part.
- The second redistribution layer in the upper structure also has a pattern that includes a line part and a via part. The width of the via part increases towards the line part from the top surface of the via part.
Potential applications of this technology:
- Semiconductor packaging industry
- Electronics manufacturing
Problems solved by this technology:
- Provides a structure for efficient redistribution of electrical connections in semiconductor packages
- Allows for increased width of via parts, improving electrical performance
Benefits of this technology:
- Improved electrical performance and signal transmission in semiconductor packages
- Enhanced reliability and functionality of electronic devices
- Simplified fabrication process for semiconductor packages
Original Abstract Submitted
Disclosed are semiconductor packages and their fabricating methods. The semiconductor package includes a lower structure and an upper redistribution layer. The lower structure includes a first bump layer, a lower redistribution layer, a semiconductor chip, a molding layer, a conductive pillar, and an under pad layer. The upper redistribution layer includes a second bump layer and second redistribution layers. The first redistribution layer includes a lower redistribution pattern including a first line part and a first via part. A width of the first via part increases in a direction toward the first line part from a bottom surface of the first via part. The second redistribution layer includes an upper redistribution pattern including a second line part and the second via part. A width of the second via part increases in a direction toward the second line part from a top surface of the second via part.
