17699756. NEUROMORPHIC MEMORY CIRCUIT AND OPERATING METHOD THEROF simplified abstract (Samsung Electronics Co., Ltd.)
NEUROMORPHIC MEMORY CIRCUIT AND OPERATING METHOD THEROF
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NEUROMORPHIC MEMORY CIRCUIT AND OPERATING METHOD THEROF - A simplified explanation of the abstract
This abstract first appeared for US patent application 17699756 titled 'NEUROMORPHIC MEMORY CIRCUIT AND OPERATING METHOD THEROF
Simplified Explanation
The abstract describes a neuromorphic memory circuit that consists of multiple memory cells. Each memory cell includes a switching element with a threshold switching time determined by the applied voltage. The switching element outputs the input signal after the threshold switching time has elapsed. Additionally, there is a resistive memory element connected to the switching element to divide the applied voltage, and a synapse circuit that generates an output signal in response to the input signal delayed by the threshold switching time.
- The memory circuit is designed to mimic the behavior of neurons in the brain.
- Each memory cell has a switching element that responds to the applied voltage and outputs the input signal after a specific time.
- The voltage applied to the switching element is divided by a resistive memory element.
- The synapse circuit generates an output signal based on the delayed input signal.
Potential Applications
- Artificial intelligence and machine learning systems
- Neuromorphic computing
- Brain-inspired computing architectures
Problems Solved
- Traditional memory circuits may not be efficient in mimicking the behavior of neurons.
- The neuromorphic memory circuit provides a more realistic and efficient way to process and store information.
Benefits
- Improved performance and efficiency in neuromorphic computing systems.
- Better replication of brain-like behavior in artificial intelligence systems.
- Potential for more advanced and intelligent computing applications.
Original Abstract Submitted
A neuromorphic memory circuit includes a plurality of memory cells, and each of the plurality of memory cells includes a first switching element having a threshold switching time determined based on a voltage applied to both ends of the first switching element at a time of receiving an input signal, and outputting the input signal in response to an elapse of the threshold switching time from a point in time at which the input signal is received; a first resistive memory element connected to the first switching element to divide the voltage applied to both ends of the first switching element; and a synapse circuit to generate an output signal in response to the input signal delayed by the threshold switching time.
