17699451. SYSTEM ON CHIP AND METHOD FOR OPERATING SYSTEM ON CHIP simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SYSTEM ON CHIP AND METHOD FOR OPERATING SYSTEM ON CHIP

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Seok Ju Yoon of Yongin-si (KR)

Eun Ok Jo of Suwon-si (KR)

Jae Joon Yoo of Incheon (KR)

SYSTEM ON CHIP AND METHOD FOR OPERATING SYSTEM ON CHIP - A simplified explanation of the abstract

This abstract first appeared for US patent application 17699451 titled 'SYSTEM ON CHIP AND METHOD FOR OPERATING SYSTEM ON CHIP

Simplified Explanation

The abstract describes a system on chip (SoC) and a method for operating it. The SoC includes multiple intellectual property (IP) cores, a buffer with multiple queues, and processing circuitry. The method involves generating traffic data from an IP core, reserving a queue in the buffer based on the traffic data, and using the reserved queue for transmitting data.

  • The system on chip (SoC) includes multiple IP cores, a buffer with queues, and processing circuitry.
  • The first IP core is designed for real-time data processing.
  • The processing circuitry generates traffic data based on the output of the first IP core.
  • At least one queue in the buffer is reserved as a dedicated area based on the traffic data.
  • The dedicated area serves as a queue for transmitting the data processed by the first IP core.

Potential Applications

  • Embedded systems
  • Internet of Things (IoT) devices
  • Mobile devices
  • Automotive electronics

Problems Solved

  • Efficient data processing in real-time
  • Effective management of data transmission queues
  • Optimization of system on chip performance

Benefits

  • Improved real-time data processing capabilities
  • Enhanced data transmission efficiency
  • Streamlined system on chip operation
  • Increased overall system performance


Original Abstract Submitted

A system on chip and a method for operating a system on chip are provided. The system on chip a plurality of intellectual property (IP) cores including a first IP core configured to process data in real-time, a buffer including a plurality of queues, and processing circuitry configured to, generate first traffic data corresponding to first data output from the first IP core, and reserve at least one queue of the plurality of queues as a first dedicated area based on the first traffic data, the first dedicated area configured to be used as a queue for transmission of the first data.