17694011. SEMICONDUCTOR DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Doyoung Choi of Hwaseong-si (KR)
Mingyu Kim of Hwaseong-si (KR)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17694011 titled 'SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a semiconductor device that includes different thicknesses of gate dielectric layers and semiconductor patterns in different regions of the device.
- The device includes a substrate with two regions, each containing active patterns, source/drain patterns, and channel patterns.
- The first region has a thicker gate dielectric layer and a thinner semiconductor pattern compared to the second region.
- The second region has a thinner gate dielectric layer and a thicker semiconductor pattern compared to the first region.
- The device also includes gate electrodes on the channel patterns and interface layers between the channel patterns and gate electrodes.
Potential applications of this technology:
- Semiconductor manufacturing industry
- Electronics industry
- Integrated circuit design and fabrication
Problems solved by this technology:
- Allows for the optimization of gate dielectric layer thickness and semiconductor pattern thickness in different regions of a semiconductor device.
- Provides flexibility in designing and fabricating semiconductor devices with varying performance requirements.
Benefits of this technology:
- Improved performance and efficiency of semiconductor devices.
- Enhanced control over the electrical properties of different regions within a semiconductor device.
- Increased flexibility in designing and fabricating complex integrated circuits.
Original Abstract Submitted
A semiconductor device includes: a substrate including first and second regions, first and second active patterns in the first and second regions, respectively; first source/drain patterns and a first channel pattern including first semiconductor patterns; second source/drain patterns and a second channel pattern including second semiconductor patterns; first and second gate electrodes on the first and second channel patterns, respectively; and a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer includes a first interface layer between the first channel pattern and the first gate electrode, and a first high-k dielectric layer. The second gate dielectric layer includes a second interface layer and a second high-k dielectric layer between the second channel pattern and the second gate electrode. A thickness of the first high-k dielectric layer is greater than that of the second high-k dielectric layer. A thickness of the first semiconductor pattern is less than that of the second semiconductor pattern
